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Papyrus | 1995-11-25 | 396KB | 2,896 lines

Courier New Swiss 721PARA Swiss 721 DIN A4 Standard Leerzeile berschrift Kommentar hlung Listing ckliste zuord Liste Liste1 c4NOTE "Ansicht ULTRA Karte "Schaltplan Anbindung Hanau Ethernet vorgestellte einer Karte basiert Karte ELITE >ULTRA (siehe Abbildung). Diese Karte zeichnet durch hervorragende Performance geeignetes Interface Diese Karte teurer 160,-) NE2000 qkompatible Karte, durch obigen Vorteile eindeutig gemacht wird. Interface andere Karten verwendet werden, wobei Beachten bwenige glichen Buszyklen unterst werden. Entwicklung Schaltung stand geringe Aufwand Vordergrund. Terreichen waren einige Kompromisse notwendig, Performance nicht geringsten glich sind! Zugriffe Schaltung sehen wurden Daten Adressleitungen beiden Bussysteme' ;einfach miteinander verbunden. Schaltplan Widerst 1.2kOhm Adressen Datenleitungen, sowie Leitungen nicht eingezeichnet. Diese ganz6 dicht angeschlossen werden. tZwei GAL's sorgen Anpassung Timings Zugriffen Busses aBus. Dabei werden Arten Zugriffen unterschieden: Memoryzugriff. erfolgt wortweiser Zugriff Cgleichzeitig. Karte beherrscht diesen Zugriff. Dabei Leitung /SBHE 'aktiviert werden, hrend Lese/Schreibzugriff erfolgt. Zugriff erfolg Adressen q$FE000000 $FE100000. Wichtig: little Endian Maschine >Datenleitungen vertauscht werden!!. Zugriff gerade Adressen. Dieser Zugriff greift geraden Adressen Karte Diese Adressen werden D0-D7 bertragen. /SBHE nicht +aktiviert, Transfer Zugriff ungerade Adressen. ungeraden Adressen Karte zugegriffen werden. Diese werden dieser D0-D7 transferiert. 68000 Merwartet diese seinen D0-D7 D8-D15 verbunden sind. Dkeinen Bustreiber verwenden ssen, wurde dieser Zugriff ebenfalls gerade M68000er Adresse gelegt. Leitung einen anderen Wert. Dieser abgeleitet. Somit Adressbereich getrennte Bereiche( gerade ungerade Bytes. Timing Timing grunds tzlich asynchron, somit recht einfach andere lTiming anpassen. Dabei Buszyklus solange ngert, Karte Daten bereitsgestellt abgeholt Dieser Vorgang gerung /DTACK Hilfe Schieberegisters (74164) durchgef Schieberegister jedem Zyklus werden aktiviert) /T_ST freigegeben, schiebt hindurch. Diese Terscheint jeweils einem Clock Impuls einen Ausgang weiter. Impulsen erreicht schlie Ausgang dadurch DTACK aktiviert, falls Karte nicht cnoch etwas fordert. gesamte Vorgang dauert 280ns, wodurch Transferrate erreicht werden kann. zeigt sich, Karte anderen Karten berlegen einem Blick Gleichungen festzustellen, Leitungen aktiviert werden. notwendig, damit Adressen lange genug mKartenzugriff stabil sind. Timing kritisch allem berhaupt nicht logisch! \urspr nglich hatte Signal erzeugt, gezeigt, berhaupt nicht notwendig ist. Interrupts Karte Interrupt praktisch wertlos, daher wurde eigene Interruptlogik zinstalliert, einen Vektorinterrupt notwendig, hkeinen Autointerrupt unterst Vektorgenerator (74LS245) dessen Vektor verdrahtet sind. beliebiger anderer freier Vektor Owerden. meinem Prototypen Schalterarray angeordnet. Logik, Erkennung tigung eines Interruptes notwendig befindet *VME_PC17. Dieses Adressen A1-A3, bekanntgibt welcher XInterruptlevel werden soll. Interface verwendet Interruptlevel Faulheit wurde Interruptkette (IACKIN/IACKOUT) nicht implementiert. Daher keine7 +andere Buskarte Interrupt verwenden. Interruptquelle Interrupt (IRQ3) Karte. Diese Leitung aktiv, tigt* 9daher einen pull-down Widerstand! VME_PC16, *IDENTIFICATION VME_PC; 7*TYPE rGAL20V8; 7*PINS [/DS0 [/DS1 -/WAIT h/DTACK.T QT_START.T /SBHE.T DA0.T /MWR.T /MRD.T /IOW.T /IOR.T *BOOLEAN-EQUATIONS= ~DTACK /WAIT; {T_START DS1);6 tSBHE /DS1); A20; N*END VME_PC173 *IDENTIFICATION rVME_PC1; 7*TYPE rGAL16V8; 7*PINS -/RESET [/DS0 D/IACK IRQ3_PC h/DTACK.T Q/VEKTOR.T /IRQ4.T :RESET_PC.T *BOOLEAN-EQUATIONS nDTACK IACK;. WVEKTOR IACK; QIRQ4 IRQ3_PC; #RESET_PC RESET; N*END ckliste- 74LS164 74LS245 UVME_PC16 UVME_PC17 D1-D3 1N4181 ?RN1-5 Widerstandsarrays 8*1.2k (nicht eingezeichnet, siehe Text) 100nF Blockkondensatoren jedem glichst mehrfach!) AUFBAU Aufbau Schaltung allem mechanische Herausforderung. Aufbau darauf Achten, Adress Datenleitungen angegebenen Pull-up Widerst versehen werden. nicht gemacht, kommt Schreibfehlern Zugriff Karte, unsch Systemabst Folge haben nnen. Schaltung einer Europa-Experimentierplatine aufgebaut. c20cm fliegenden Leitungen angeschlossen. Tower wohnt keine Aussagen& Originalgeh treffen. Falls schon einer Grafikkarte belegt etwas einfallen lassen, Veinen weiteren erhalten. einfach bestehenden parallel geschaltet werden. Interface eigentlich 64-polige Verbindung Reihe), mittlere Pinreihe VME-Bus (fast) nicht wird. IRQ-4 Leitung >einzige, mittleren Pinreihe liegt! yFalls Adresskonflikten einer anderen Karte kommen sollte VME_PC16< oumprogrammiert werden (Auswertung A23). Konfigurieren Karte Karte beitzt einen einzigen Jumper, Stellung NONE" gebracht wird. Tests Software sollte mindestens RAbschlu widerst Connector gesteckt werden. Karte besitzt Netzaktivit anzeigt. Hardware Einschalten, sowie einem Reset (CTRL-ALT-DEL Akivit Karte aufleuchten einigen Sekunden wieder schen. Damit Reset schon Ordnung. pBevor Treiber installiert Hardware werden. Debugger Monitor (z.B. Debugger). diesem Monitor Adresse $FE200280 beobachtet. sollte jedes sein. $FE2002A0 sollten wieder KBytes sein, obigen Adresse. Dieses Verhalten Adresse $$FE300280 feststellbar sein, wobei andere Werte stehen ssen. Durch wechselseitiges zusammensetzen Bytes Karte aufgedruckte Ethernetadresse erkennbar cwerden. erfolgreich, Treiber installiert werden. Software Software besteht einem Treiber (Atari Network System). Dieser Treiber stellt einfache Funktionen lesen schreiben Datenpaketen gung. Einbindung" qerfolgt Cookie. Treiber wurde TCP/IP Stack sowie Telnet getestet. TGegenstelle dient LINUX MAG!C eingesetzt, Plain sollte genauso gehen. wird's wahrscheinlich nicht funktionieren (hab's nicht getestet). %Damit jeder sehen kann, Karte angesteuert wird, Paket Sourcen Treibers cbeigelegt. PURE-C sollte bersetzen Problem sein. WD_TOOLS.C Initialisierung Karte eingesehen werden, falls Vorgang Testzwecken+ %manuell durchgef werden Hinweise Angaben dieses Paketes durch Betrieb Aufbau Scahltung Soder Software entstehende keine Haftung bernehmen. Betrieb `eigene Gefahr Risiko. Weitergabe Verwendung dieses Dokumentes zugeh rigen Software frei. PFalls jemand Schaltung erfolgreich aufgebaut falls Fragen bestehen, stehe egerne weitere Fragen gung. setzte jedoch voraus, Erbauer dieses Interfaces etwas Erfahrung Umgang Oszilloskop ansonsten OFerndiagnose vollkommen sinnlos. Falls jemand Fehler findet, bitte ebenfalls Nachricht,7 9damit diese Paket korrigieren kann. jedoch keine Platine fertig gebrannte GAL's geben nicht diese vertreiben. Falls jemand Platine erstellt bitte Nachricht,. $denn gerne Pinbelegungen Platinenprogramm nummeriert eines Steckers fortlaufend durch. Somit ergebn folgende Zuordungen: a1-a32 b1-b32 33-64 c1-c32 65-96 A1-A31 32-62 B1-B31 1-31 C1-C18 19-36 D1-D18 1-18 Adressen Sackpost: Ulrich Gustav Adolf 63452 Hanau *Maus: Ulrich Roehr WInternet: ulrich_roehr@f.maus.de vANHANG Signalbeschreibung output signal inactive (low) indicates controller board master control active, controller control often disable devices which respond during cycle. output signal (when high) indicates valid address present LA<23..I7> maddress lines. LA<23. address lines decodes developed should [latched falling BALE. master operation occurring. &BCLK output signal provided allow synchronization processor clock. freguency either cycle \BUSR0Y input signal lengthen cycle standard controller board Ocannot respond guickly enough. should pulled collector device soon addressed device selected until device responded. cycles lengthened integral number (BCLK) cycles. should should driven oPen-collector device capable sinking DAK0- WDAK1- WDAK2- WDAK3- WDAK5- WDAK6- DAK7- These output lines Acknowledge) indicate reguest service subsystem recognized. acknowledge indicated line. l0RC- I0WC- decode desired device. signal acceptance bus-master reguest, signal indicates legal GRAB- !DRQ2 !DRQ3 !0RQ5 !0RQ6 These input lines request service subsystem ccontrol system request). request HIine remain until appropriate DAK<7. active. dGRAB- input signal indicate controlIer board master controlling controlIer board appropriate active, signalIing master request granted. system address, controI lines floated, @allowing controller board begin controlling period after \made active. Ieast period should allowed after putting vaIid \address before activating controI lines. should driven open-collector device capabIe sinking GROUND These lines connected system ground. maximum current allowed singIe contact IOCHK- input signal signaI about Parity other serious errors controller 1boards. signal should driven colIector output capabIe sinking; uncorrectabIe system error occurs. lORC- output read) indicates (when device driven controller board acting master. I0WC- output write) indicates (when device accept driven controlIer board acting master. l016- input bits) signaIs system addressed device capable Htransferring once. active, during write, standard state cycle should driven open-colIector device canabIe sinking !IRQ6 !IRQ7 !IRQ9 !IRQ10 !IRQ11 lRQ12 lR014 IRQ15 These input lines interrupt request service. interrupt |recognized remains there until appropriate1 interrupt service routine executed. 4LA18 4LA2D 4LA21 4LA22 These output signals (LatchabIe Address) decode memory which respond state. guaranteed valid high. These driven controller board acting master. MRDC- output (Memory Read) indicates (when memory device signaI active entire address space system. driven controIler board acting master. MWTC- output (Memory Write) indicates (when memory device accept %data signal active entire address space system. driven controIler board acting master. @MI6- input (memory bits) signais system addressed memory capabIe itransferring once. active, during memory Twrite, standard state memory cycle shouId derived LA<23. address Iines. shouId driven collector device$ capabIe sinking TN0WS- input State) inform system standard states +deleted cycIes active. pulled before Nfalling order recognized. shouId driven cpen5 collector device capabIe sinking output signai cIock video color burst other general timing applications. frequencv I4.3I8I8 cycle approximateIy VREFRESH- output signal indicate (when refresh cycle progress. shouid enabIe SA<7. address lines address inputs banks dynamic 5memory MRDC- active, entire system memory refreshed time. driven controIier board acting master. RESDRV output signal reset hardware during powerup power failure. 4SAI0 4SAlI 4SAl2 4SAl3 4SAl4 4SAl5 4SAI6 4SAI7 4SAl8 These bidirectionaI signals address memory devices within system. order address system offers. These lines enabled while latched state. These driven controlIer board acting master. ?SBHE- output signal (System Enable) indicates (when data should transfer boards which support l6-bit driven controller board actinq master. These bidirectional signals system should Zexclusively eight devices transfer data. Sixteen-bit devices should these lines transfer address These driven controIIer board acting master. 4SD09 4SD10 4SD11 4SD12 4SD13 These bidirectional signals system Sixteen devices {should these lines transfer SBHE- These driven controller board acting master. SMRDC- output (Standard Memory Read) active (low) address 000000h 0FFFFFh decoded. derived MRDC-. /SMWTC- output (Standard Memory Write) active (low) address 0000000h 0FFFFFh decoded. derived MWTC-. output signal (when high) indicates Terminal Count operation reached. should decoded appropriate proper operation. connected system power supply minus volts. supply intended0 low-current usage connected system power supply minus volts. supply intended. low-current usage connected system power supply voIts. addition maximum current available suppIv, maximum current aIlowed contact <<88<8<<8 <8<888< <8<888 <88<88 <88<88<88 <88<88 <88<<8 88<8<<88< <|<|<<<<|<|<|<<|<<||< <|<<|<| |<x<< |<<||< <|<||<<<|<| <88<88<88<88 8<<<||8 8<<<8|||<<<< |x88<88|8< )<<|||<||||<|||<|||<||<<||<<||<<|<<<<|<<<| ||<<| 8<<88<8 |x<8<x<|8 <||<| <<88< <><<< ||<<8<8<||8<||||8<8<<||x8<|<|<< 8<<<<8 ~~|~~ <<8<<88< <8888 888<8 88<<< <<|88<8<<|88<<<<|<<|< <8<|||~|8<~ <<<<| <888<88< <88<<<888 88<<< <|<|<x888<<|8888<<|8<88< <|||< <||<<||<||||< |88<8<|||~|8<~||~~|||| <<<<| |<<<||<<< 8<<88<8 8<<<88 888<?<<8 <<<=<88 88<<< |~~|~~||~|~~|~~||~|~~||~|~~ ~~|~|||~ |~~|| 8<8<8<8<|||~~~|| 8888<8 ||<<<<|||<< <?>><> <8888<8 <???<< 8<<<<>88 88<<< <|8<|| |~~||||~~| ~|<|||<<<||>~ x||||< <||<|||<<<||< <<|<|<< ||<|<<< 8<8<~|8 |<||<<|<<| ||<<<<8<<<< |<||< 8>8?>8? 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